1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration for reducing a test time required in a semiconductor memory device having a plurality of data input/output terminals.
2. Description of the Background Art
FIG. 11 shows a pin arrangement in a conventional semiconductor memory device 9000. In FIG. 11, a reference character Q represents a pin. Each of pins Q represents an address pin, a data pin, a control signal pin, or one of a plurality of data I/O pins.
In a semiconductor memory device (especially SRAM as semiconductor memory device 9000, all data input/output pins must be used in order to test its internal operation. If there is 36 data input/output pins, for example, data must be written into and read out from all of 36 data input/output pins and signals output from corresponding pads must be measured.
Especially when the number of I/O pins increases, as signal application and output measurement is required for all I/O pins, the configuration of a testing apparatus (probe) becomes complicated. In addition, with a large number of I/O pins, the number of chips (semiconductor memory devices) which can be measured at one time is limited. Thus, a simultaneous testing of a large number of chips is not allowed, which leads to a long test time and a large test cost.